1. Field of the Invention
The present invention relates to memory circuits for data processing. More particularly, this invention relates to reducing static power consumption in such memory circuits.
2. Description of the Prior Art
Complementary metal-oxide semiconductor (CMOS) transistors are the current technology of choice for most data processors due to their advantageous characteristic of consuming power only when switching. When not switching, individual CMOS transistors consume a negligible amount of power (˜10−15 Amps for N-type or P-type transistor) although the cumulative leakage current for modern data processors which have high transistor densities is becoming more and more significant as component sizes shrink and transistor densities increase (˜10−6 Amps). It is estimated that static power consumption currently accounts for 15% to 20% of the total power on chips implemented in high-speed processes.
The total power consumption in a CMOS circuit includes a dynamic power component, Pdynamic, due to switching activity and a static power component, Pstatic, arising from transistor leakage current. Pdynamic has a contribution from each switching event of C Vdd2 f, where C is the gate output capacitance and f is the processor clock frequency. Whereas Pstatic=IleakageVdd, where: Ileakage is the total chip leakage current and is proportional to e(−Vt/T); T is the temperature; and Vdd is the power-supply voltage. Accordingly, as Vt decreases Ileakage rises dramatically.
Reduced power supply voltages have accompanied decreasing feature dimensions in successive generations of silicon process technologies. These reduced supply voltages have tended to offset the impact of increasing transistor counts and increasing clock frequencies on dynamic power. As power supply voltages decrease, it is necessary to decrease transistor threshold voltages Vt to maintain fast switching speeds and sufficient noise margins. However reduced power supply voltages Vdd result in increased static power consumption.
FIG. 1 of the accompanying drawings is a graph of normalized leakage power against minimum transistor gate length in μm (10−6 m) for four different temperatures. The data were obtained from a circuit simulation. This graph illustrates that as processor technology moves below 0.1 micron, static power consumption, if left unchecked, is set to increase exponentially and could conceivably dominate the total power consumption of the central processing unit (CPU).
One known technique to reduce static power consumption is the gated-VDD technique as introduced in M. Powell et.al. “Gated-Vdd: A circuit technique to reduce leakage in deep submicron cache memories”, Proc. Of Int. Symp. Low Power Electronics and Design, 2000, pp.90-95. Memory circuits of this type are settable to either a full-power mode or a low-leakage mode. The gated-VDD technique reduces the leakage power by employing a high threshold (high-Vt) transistor to turn off the power to the memory cell when the cell is set to a low-leakage mode. This high-Vt device drastically reduces the leakage of the circuit because of the exponential dependence of leakage current on Vt. Although the gated-VDD technique is very effective at reducing leakage current, its main disadvantage lies in that it loses any information stored in the memory cell when switched into low-leakage mode. In the case of an on-chip (L1) cache memory circuit this means that the lost data must be reloaded from off-chip (L2) cache if the data is to be retrieved and this tends to negate energy savings as well as incurring a significant performance penalty. To avoid these drawbacks, gated-VDD schemes must use complex adaptive algorithms and be conservative about which arrays of memory cells (such as cache lines) are turned off.
A second known technique for reduction of static power consumption is adaptive body-biasing with multi-threshold CMOS (ABB-MTCMOS) as described in K. Nii, et. al. “A low power SRAM using auto-backgate-controlled MT-CMOS”, Proc. of Int. Symp. Low Power Electronics and Design, 1998, pp. 293-298. Again, each cell of this memory circuit is settable to either a full-power mode or a low-leakage mode. In this case the low-leakage mode does not involve completely switching off power to the transistors, rather transistors are set to a low-power “drowsy mode” in which leakage power is reduced. The drowsy mode is implemented by dynamically increasing the threshold voltage of the transistor memory cells. This paper by Nii et. al., discloses an static random access memory (SRAM) circuit in which an active mode is achieved by setting a first virtual source line to 1.0V (via a first PMOS transistor) whilst a second virtual supply line is forced to ground level (via an NMOS transistor). In the active mode the voltage source is set at 1.0V. This can be contrasted with a sleep mode where the first virtual source line is set to the higher value of 2.3V whilst the second virtual source line is also increased from ground to 1.0V. In sleep mode the voltage source is increased to 3.3V and two pairs of diodes are used (each diode having a forward bias of 0.5V) to obtain the 2.3V and 1.0V virtual supply levels. Although the leakage current through the memory cell is reduced significantly in this ABB-MTCMOS scheme, the necessary increase in the supply voltage of the circuit in sleep mode acts to offset some of the gain derived from the reduction in total static power consumption. Accordingly the leakage power in the low-leakage mode is much higher than that achievable by switching off the transistors.
Furthermore, this ABB-MTCMOS technique requires that the voltages of both the power and ground supply lines in addition to the voltage of the N-wells are changed each time the circuit enters or exits drowsy mode. The substantial N-well capacitance of the PMOS devices increases the energy required to switch the cache memory cell to high-power mode and can also significantly increase the time needed to transition to/from drowsy mode. Since the ABB-MTCMOS technique involves changing the substrate voltages of the PMOS transistors it would be very difficult to implement other than on a cell by cell basis in memory. Similarly to the above-described gated-VDD technique, ABB-MTCMOS requires special high-Vt devices for the control logic.
Accordingly, there is a need for a memory circuit that offers better leakage power reduction and faster switching than ABB-MTCMOS type circuits yet is simple to implement (e.g. line by line in cache memory) and retains cell information in the low-leakage mode.